c2duo

The Core 2 brand refers to a range of Intel's consumer 64-bit dual-core and MCM quad-core CPUs with the x86-64 instruction set, and based on the Intel Core microarchitecture, which derived from the 32-bit dual-core Yonah laptop processor. (Note: The Yonah had two interconnected cores, similar to those branded Pentium M, but comprising a single silicon chip or die.) The 2x2 MCM dual-die quad-core CPU had two separate dual-core dies (CPUs) - next to each other - in one quad-core MCM package. The Core 2 relegated the Pentium brand to a lower-end market, and reunified the laptop and desktop CPU lines divided into the Pentium 4, D, and M brands.The Core microarchitecture returned to lower clock speeds and improved processors' usage of both available clock cycles and power compared with preceding NetBurst of the Pentium 4/D branded CPUs. It translates into more efficient decoding stages, execution units, caches, and buses, etc, reducing the power consumption of Core 2 branded CPUs, while enhancing their processing capacity.The Core 2 brand was introduced on July 27, 2006comprising of the Solo (single-core), Duo (dual-core), Quad (quad-core), and Extreme (dual- or quad-core CPUs for enthusiasts) branches, during 2007.The Core 2 Memory management unit (MMU) in X6800, E6000 and E4000 processors does not operate to previous specifications or implemented in previous generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with existing operating system software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the Translation Lookaside Buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, e.g. hangs or incorrect data."Among the issues noted:Write-protect or non-execute bit for a page table entry is ignored.Floating point instruction non-coherencies.Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.Intel errata Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious. 39, 43, 79, which can cause unpredictable behavior or system hang, have been fixed in recent steppings.Among those who have noted the errata to be particularly serious are OpenBSD's Theo de Raadt and DragonFly BSD's Matthew Dillon. Taking a contrasting view was Linus Torvalds, calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better."With the release of the new Core2 processor, the abbreviation C2 has come into common use, with its variants C2D (the present Core 2 Duo), and C2Q, C2E to refer to the Core 2 Quad and Core 2 Extreme processors respectively. C2QX stands for the Extreme-Editions of the Quad (QX6700, QX6800, QX6850).